Packaging technology for Integrated Circuits (IC) in the semiconductor industry undergoes increased development in order to satisfy a need for miniaturization and/or mounting reliability. Wafer level processing (WLP) techniques have been developed to allow various features of IC packages to be formed within a wafer before the wafer is diced. For instance, certain WLP techniques are used to form device interconnection features together with other wafer processing steps, thereby avoiding the need to form wire bonding after IC chips are diced.
In general, such WLP techniques allow IC package manufacturing processes to be streamlined and consolidated. Moreover, WLP techniques can generally be performed in parallel on a plurality of IC chips arranged in a matrix on the wafer, thereby allowing a plurality of IC chips to be formed and tested while still in a wafer stage. By performing WLP techniques in parallel across a plurality of IC chips, IC package manufacturing throughput is increased and the total time and cost required to fabricate and test IC packages is decreased accordingly. In addition, by forming features such as device interconnections at the wafer level, the overall size of IC packages can be reduced.
One of the WLP techniques used to form device interconnections involves the formation of a through silicon via. A through silicon via (TSV) is usually formed by creating a hole (via-hole) through a semiconductor substrate and/or various material layers formed on the substrate, and then forming a penetration electrode in the hole. The penetration electrode may be connected to internal features of an IC chip such as signal terminals, data transmission lines, transistors, buffers, and so on. In addition, the penetration electrode may be connected to features external to the IC chip, such as a PCB, via an external terminal.
Depending on the type of process in use, via-holes could be formed in different layered stacks of materials in wafers and other substrates. The holes are typically formed by etching based on Reactive Ion Etching (RIE) or laser drilling by ablation. The ion etching can be performed by a variety of processes optimized for materials, etch rate, sidewall slope, smoothness and other parameters. A well known method of etching is the Bosch method which is based on alternating steps of semi-isotropic etching and deposition.
In the so-called “via-first approach”, the holes are first formed in silicon, by etching using an etch mask and photoresist and/or other harder mask materials. The mask materials layers are relatively thin layers on thick silicon. If the via-holes are formed by laser-drilling, no etch mask material is used, the holes being formed only in the thick silicon. Via-hole diameters can range from the one micron scale up to tens of microns, with depth to diameter aspect-ratios going from 5 or less up to 30 or more. The minimum pitch that can be implemented between the holes is a critical parameter for minimizing the distance that electrical signals have to cover between the vertically stacked ICs. The minimum pitch is usually a small multiple of the minimum hole diameter.
In the so-called “via-last approach”, the holes are formed in the wafer backside through the silicon, until coming up to the conductive material on the wafer frontside. In this case, in addition to the possible etch mask materials on the silicon as in the via-first, the bottom of the hole (i.e. near to the wafer frontside) is formed in a different, possibly conducting, material such as copper. The layered stack can thus include possible masking layers, silicon sidewalls and a conductive bottom.
An additional option for the via-last approach is based on etching or laser drilling through the full stack of materials on the wafer frontside including dielectric insulating materials. The bottom of the hole is deep in the silicon substrate. The layered stack can include in this case, possible masking layers, sidewalls of various dielectric materials, sidewalls of silicon and bottom of silicon. In via-last, the holes are usually formed with dimensions and pitch (e.g. tens of microns) larger than in the via-first, usually targeted to be connected with the underside of previously formed copper pads on the front surface of the wafer.